1. Field of the Invention
The present invention generally relates to a circuit for setting conditions for giving a central control circuit access to a read-write memory (RWM) and, more particularly, to a memory write protection circuit for establishing predetermining conditions under which a CPU may write data in an RWM.
2. Description of the Prior Art
Electronic equipment or system of the kind using RWM is in many cases furnished with a write protection circuit for preventing data from being destroyed due to careless or erroneous accesses to the RWM. Specifically, the write protection circuit inhibits the writing of data in the RWM unless a predetermined procedure is performed on a data processing unit.
FIG. 1 shows an example of a memory map in this kind of systems. In the drawing, the RWM is divided into some areas which include a particular area that inhibits write-in except when a predetermined procedure is performed (hereinafter referred to as a DTMP area) and an area which is freely accessible for write-in (hereinafter referred to as a WE area).
Referring to FIG. 2, a prior art protection circuit is shown which includes a decoder 30 for designating the DTMP area. The DTMP area is set up only when the logic of an address entered via an address bus and the logic set in the decoder 30 beforehand are coincident, i.e., it is determined by the hardware of the decoder 30.
The CPU delivers an I/O (Input/Output) read signal IOR, an I/O write signal IOW and address to an order developing circuit 31. In response, the order developing circuit 31 produces a first input command (IN1) and a first output command (OUT1, where DO="H") on the basis of the combination of the three inputs.
To cancel write protection, the two different commands IN1 and OUT1 are produced eight times alternately. This sets and resets an SR flip-flop 34 eight consecutive times, turning an output Q.sub.4 of a counter 40 from low level or "L" to high level or "H". The change in the output Q.sub.4 of the counter 40 appears as data DO which is sent via an inverter 41, a switch 42 and a 3-state buffer gate 46. The CPU scans for such data DO by using the input command, or read command, IN1. Subsequently, when an address for memory access is entered, the decoder 30 produces an output ("H"). This decoder output and the output Q.sub.4 of the counter 40 turns the output of an AND gate 44 from "H" to "L", resulting in a memory write signal MWR becoming valid via an OR gate 45.
Consequently, write protection is cancelled to allow a write enable signal WE to be fed to the RWM. The turn of the output Q.sub.4 of the counter 40 to sends a signal through invertor 41 and OR gate 38 to change the CLR input of counter 37 from "H" to "L" and start counting clock pulses (250 kilohertz). As 32 milliseconds expire, the output Q.sub.14 of the counter 37 becomes "H". Then, the counter 40 is reset via an inverter 36 and NAND gate 39 so that the DTMP area is again protected against the write-in of data.
When data is written in the DTMP area while the protection is cancelled, the signal MWR resets the counter 37 via an inverter 32, an AND gate 33, and the OR gate 38, thereby causes counter 37 to again start counting from 0 (zero). As a result, the write protection cancelling time is prolonged.
Conversely, when the first output command (OUT1, where DO="L") is entered, it will clear the counter 40 via an OR gate 35 and a NAND gate 39 to set up the protection immediately. Further, when the switch 42 is brought to an OFF state, the DTMP area designated by the decoder 30 will turn out to be a WD area which does not allow any data to be written therein even when the protection cancelling procedure (stated above) is performed.
The prior art protection circuit having the above construction has some problems which are left unsolved. Specifically, since the DTMP area is determined by the logic which is set up by the decoder 30, the allocation of areas in the RWM is unchangeable, i.e., it lacks flexibility. This obstructs the efficient use of the RWM in the event of software program construction in the CPU, due to the limitation on the use of the areas of the RWM. Another problem is that only one of the DTMP and WD areas can be set up at a time. Moveover, they are changed over by the switch 42, resulting in unflexible and inefficient manipulations.